To achieve high-speed, low-power read operations of Static Random Access Memories (SRAM) built in the semiconductor integrated circuit device, small-amplitude bit-lines (BL) and clocked sense-amplifiers are employed. For the reliable operation at high-speed, however, the sense-amplifier enable (SAE) signal must track delay fluctuations of global and local processes, voltage, and temperature (PVT) at the small-amplitude bit-lines (BL). If the sense-amplifier enable (SAE) signal is activated before a differential bit-line signal exceeds a sense-amplifier offset, a read failure may occur at a sense-amplifier output. Conversely, if the activation of the sense-amplifier enable (SAE) signal delays too far, then an access time and power consumption increase unnecessarily.
Umut Arslan et al, “Variation-Tolerant SRAM Sense-Amplifier Timing Using Configurable Replica bitlines”, IEEE 2008 Custom Integrated Circuits Conference (CICC) 21-24 Sep. 2008, PP. 415-418 (Non-Patent Document 1) discloses that replica bit-lines (RBL) track delays of the bit-lines (BL) better than simple buffer chains regarding global (PVT) skews, and accordingly a self-timing of the sense-amplifier enable (SAE) signal is set using the replica bit-lines (RBL) in the SRAM. In the SRAM, replica word lines (RWL), replica memory cells, the replica bit-lines (RBL), dummy memory cells, and inverters are disposed between a word decoder and the sense-amplifiers. The replica word lines (RWL) generated from the word decoder in response to a clock signal by the read operations are asserted, whereby a plurality of replica memory cells are turned on so as to discharge the replica bit-lines (RBL) connected to the negative dummy memory cells. Full-amplitude replica bit-line (RBL) signals are inverted by the inverter and are buffered, whereby the generated sense-amplifier enable (SAE) signal is supplied to the sense-amplifiers. The replica bit-line (RBL) signal can be also used for both limiting a bit-line amplitude and deactivating the word lines for power saving. The read current of the memory cells on the same semiconductor die is correlated by global PVT fluctuations, whereby good tracking of the delays of the replica bit-lines (RBL) and the delays of the bit-lines (BL) is made possible.